1. Field of the Invention
The present invention relates to an input buffer circuit for a semiconductor memory, and particularly to an input buffer circuit of a semiconductor memory capable of controlling a logic threshold voltage of the circuit according to a change in an external voltage.
2. Description of the Conventional Art
An input buffer circuit, directed to changing an externally inputted voltage of TTL level into a voltage of CMOS level, generally includes NOR gates, NAND gates, or inverters. Further, the input buffer circuit is enabled by a chip selection signal CS determining an operation of the circuit, and outputs a signal Buffer Output of CMOS level by converting an input signal Buffer Input of TTL level.
Referring to FIG. 1, the conventional input buffer circuit includes PMOS transistors 11 and 12, and an NMOS transistor 13 connected in series between an external voltage VCC and ground; an NMOS transistor 14 having its source grounded, and its drain connected to a common connecting point between the PMOS transistor 12 and the NMOS transistor 13 via a node N1; series inverters 15 and 16 for successively inverting the electric potential at the node N1, successively; and an inverter 17 for inverting the inputted chip selection signal CS and applying the inverted signal to the respective gates of the PMOS transistor 12 and the NMOS transistor 14. Here, the input signal Buffer Input, that is, the voltage of TTL level is applied to the gates of the PMOS transistor 11 and the NMOS transistor 13.
The operation of the conventional input buffer circuit having the above-described structure will be explained as follows. First, when the chip selection signal CS of low level is inputted, the inverter 17 inverts this signal to a high level and applies the inverted signal to the gates of the NMOS transistor 14 and the PMOS transistor 12, thereby causing the NMOS transistor 14 to be turned on and the PMOS transistor 12 to be turned off. Accordingly, the electric potential at the node N1 due to the NMOS transistor 14 which is turned on becomes low, regardless of the level of the input signal Buffer Input.
On the other hand, when a chip selection signal of high level is inputted, the inverter 17 inverts this signal to a low level and applies the inverted signal to the gates of the NMOS transistor 14 and the PMOS transistor 12, thereby causing the NMOS transistor 14 to be turned off and the PMOS transistor 12 to be turned on. Therefore, the level of the electric potential at the node N1 is decided by the input signal. Assuming that the input signal is low, the PMOS transistor 11 is turned on and the NMOS transistor 13 is turned off, and thereby the electric potential at the node N1 becomes high by the PMOS transistors 11 and 12 which are turned on. Consequently, as the electric potential at node N1 is inverted successively by the inverters 15 and 16, the output signal is high. However, when the input signal is high, the PMOS transistor 11 is turned off and the NMOS transistor 13 is turned on, and thereby the electric potential at node N1 becomes low. Since this electric potential of low level is inverted by the inverters 15 and 16, successively, the output signal becomes low. Accordingly, when the chip selection signal is high, assuming that the input signal is low, the output signal becomes high. On the other hand, assuming the input signal is high, the output signal becomes a low level.
FIG. 2 is a timing diagram showing the above-described operation. As shown in FIG. 2, when the chip selection signal CS is low, the output signal Buffer Output is always low, regardless of the level of the input signal Buffer Input. However, in the case that the chip selection signal is high, when the input signal is high, the output signal becomes low. On the other hand, when the input signal is low, the output signal becomes high.
FIG. 3 is a diagram showing the relationships between the input signal Buffer Input, that is, the voltage VBI of TTL level and the output signal Buffer Output, that is, the voltage VN1 of CMOS level at node N1, in accordance with the change of the external supply voltage VCC, in the conventional circuit of FIG. 1. Here, crossing points between the plots showing the external voltage VCC and VBI are logic threshold voltages of the input buffer circuit at each external supply voltage VCC level. When the external supply voltage is 2.6 V, the logic threshold voltage bemomes above 1 V. When the input signal is above 1 V, it is recognized as a high level, and thereby the output signal of the input buffer circuit becomes low. On the other hand, when the input signal is below 1 V, it is recognized as a low level, and thereby the output signal of the input buffer circuit becomes high. Further, when the external supply voltages are 3.3 V or 4.0 V, the logic threshold voltages become about 1.3 V or 1.8 V, respectively. When the input signals are above the logic threshold voltages, they are recognized as signals of high level, and thereby the output signals of the input buffer circuit become low. On the other hand, when the input signals are below the logic threshold voltages, they are regarded as signals of low level, and thereby the output signals of the input buffer circuit become high.
Accordingly, in the conventional input buffer circuit, there is a problem in that as the level of the external supply voltage increases, the logic threshold voltage of the circuit also increases, and on the other hand, as the level of the external supply voltage decreases, the logic threshold voltage also decreases.